Jie Lou
About Me
I am a PhD candidate at Chair of Integrated Digital Systems and Circuit Design (IDS), RWTH Aachen University, Germany, supervised by Prof. Tobias Gemmeke. I received my M.S. degree in Integrated Circuit Engineering from Tianjin University, China in 2019 and B.S. degree in Electrical Engineering and Automation from Northeast Electric Power University, China in 2016.
My master’s research focused on microwave dielectric ceramics in circuit materials and devices. During my PhD studies, I transitioned to the field of integrated circuit design. My current research focuses on time-domain compute-in-memory and its associated energy-efficient hardware design for machine learning and digital signal processing applications. I am passionate about low-power neural network accelerators and hardware-software co-design.
On the hardware side, I am proficient in ASIC design flow from transistor level design to front-end RTL, back-end P&R, and silicon measurements. On the software side, I am familar with neural network training, pruning and quantization. Currently, I have three chip tapeout experience with multiple designs on 22nm FDSOI technology, covering both standard digital design and mixed-signal approach.
I am currently on the job market and seeking opportunities as a research scientist or ASIC/SoC design engineer. Please feel free to reach out if you are interested.
News
- 2025.04.30 Our mixed-fidelity TDCIM CNN work accepted by GLSVLSI.
- 2025.03.15 One co-authored paper on uniform pruning accelerator accepted by COOL Chips.
- 2025.01.22 My PhD thesis research accepted by DATE PhD Forum.
- 2025.01.20 Our all-digital TDCIM CNN work accepted by ISCAS.
- 2024.06.21 One co-authored paper on dual-engine accelerator accepted by SOCC.
- 2024.04.08 We have submitted the 3rd test chip for fabrication using 22nm FDSOI technology.
- 2024.01.16 One co-authored paper on domain comparison accepted by ISQED.
- 2023.12.20 Invited to give a talk at Peisu Xia Forum hosted by ICT.
- 2023.10.13 I participated Beijing Tour for Overseas Talents program.
- 2023.10.03 Our all-digital TDCIM work accepted by TCAS-I.
- 2023.08.04 One co-authored paper on DSC accelerator accepted by VLSI-SoC.
- 2023.07.07 Check out Prof. Gemmeke’s Time-Domain Computing talk on YouTube.
- 2023.06.07 I presented our scalable TDCIM BNN work at the GLSVLSI in Knoxville, TN, USA!
- 2022.12.21 Check out Time Domain Compute-in-Memory news in NEUROTEC project.
- 2022.09.22 I presented our all-digital TDCIM BNN work at the ESSCIRC in Milan, Italy!
Publications [ Google Scholar]
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Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), 2025.
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IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2025.
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IEEE International Symposium on Circuits and Systems (ISCAS), 2025.
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2024 IEEE 37th International System-on-Chip Conference (SOCC), 2024.
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International Symposium on Quality Electronic Design (ISQED), 2024.
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IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2023.
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IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC), 2023.
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ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2023.
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Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), 2023.
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IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2022.
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IEEE European Solid State Circuits Conference (ESSCIRC), 2022.
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International Symposium on Quality Electronic Design (ISQED), 2022.
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Journal of Alloys and Compounds, 2019.
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Journal of Materials Science: Materials in Electronics, 2018.
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Journal of Alloys and Compounds, 2018.
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Journal of Materials Science: Materials in Electronics, 2018.
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Ceramics International, 2018.
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Journal of Alloys and Compounds, 2018.
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Journal of Materials Science: Materials in Electronics, 2018.
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Ceramics International, 2017.
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Ceramics International, 2017.
During PhD
During Master (microwave dielectric ceramics)
Internship Experience
Institute of Computing Technology, Chinese Academy of Sciences
- 2019.05 - 2019.07
- Research on SV/UVM-based RISC-V processor verification method
Analog Devices, Inc., Beijing
- 2017.12 - 2018.05
- Build module-level verification platform based on UVM
- Develop testcases & covergroups that align with the verification plan
Invited Talks
- 2023.12.20 @ Peisu Xia Forum, Beijing, China. Time-Domain Compute-in-Memory
- 2023.06.07 @ GLSVLSI, Knoxville, TN, USA. Scalable Time-Domain Compute-in-Memory BNN Engine with 2.06 POPS/W Energy Efficiency for Edge-AI Devices
- 2022.09.22 @ ESSCIRC, Milan, Italy. All-Digital Time-Domain Compute-in-Memory Engine for Binary Neural Networks with 1.05 POPS/W Energy Efficiency
Honors & Awards
- Tianjin University Outstanding Graduates, 2019
- Tianjin University Student Science Award, 2018
- Top Ten Outstanding Youth of School of Electronic Information Engineering (Tianjin University), 2018
- China National Scholarship, 2017 & 2018
Teaching
Supervised Students
- Ioannis Andrianopoulos(Bachelor), 2023 - 2024
- Marcel Pape(Bachelor), 2023 - 2024
- Chen Zhang(Master), 2023 - 2024
- Chuang Zeng(Master), 2023
Lectures
- Computer Arithmetic – Fundamental (2019 - 2023), RWTH Aachen University
- Computer Arithmetic – Advanced Topics (2024), RWTH Aachen University
- VLSI Design for Digital Signal Processing - Fundamentals (2024), RWTH Aachen University
Services
- Reviewer of IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC)
- Reviewer of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)
- Reviewer of IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)
Miscellaneous
- I am the finisher of four marathons(PB 4:17:13).
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